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NXP Semiconductors /LPC408x_7x /ADC /INTEN

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Interpret as INTEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)ADINTEN0 0 (DISABLE)ADINTEN1 0 (DISABLE)ADINTEN2 0 (DISABLE)ADINTEN3 0 (DISABLE)ADINTEN4 0 (DISABLE)ADINTEN5 0 (DISABLE)ADINTEN6 0 (DISABLE)ADINTEN7 0 (CHANNELS)ADGINTEN 0RESERVED

ADINTEN2=DISABLE, ADINTEN3=DISABLE, ADINTEN6=DISABLE, ADGINTEN=CHANNELS, ADINTEN5=DISABLE, ADINTEN1=DISABLE, ADINTEN0=DISABLE, ADINTEN4=DISABLE, ADINTEN7=DISABLE

Description

A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.

Fields

ADINTEN0

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 0 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 0 will generate an interrupt.
ADINTEN1

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 1 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 1 will generate an interrupt.
ADINTEN2

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 2 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 2 will generate an interrupt.
ADINTEN3

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 3 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 3 will generate an interrupt.
ADINTEN4

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 4 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 4 will generate an interrupt.
ADINTEN5

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 5 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 5 will generate an interrupt.
ADINTEN6

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 6 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 6 will generate an interrupt.
ADINTEN7

Interrupt enable

0 (DISABLE): Completion of a conversion on ADC channel 7 will not generate an interrupt.

1 (ENABLE): Completion of a conversion on ADC channel 7 will generate an interrupt.
ADGINTEN

Interrupt enable

0 (CHANNELS): Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts.

1 (GLOBAL): The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data